Efficient Design of Error Recovery and Improve the Performance Using Mesh of Ring Topology Based NoC

Abstract

generally, the System-on-chips (SoCs) is usually an Integrated Circuit in which integrates new elements in a single chip. Because of rise in number of transistors on a single chip gives complex system. To reduce the system complexity integrated SoC within a system, it forms a Network on Chip (NoC). Designed for NoC architectures, high performance efficient router design having minimal power consumption are necessary for real-time applications. NoCs having mesh and Ring structured interconnection topologies now are popular for their simple structures. In this paper, we designed the energy-efficient however high performance approach to conventional Hybrid mesh based-Ring using deflection on-chip networks. Most of us try to achieve the scalability associated with meshes by the router simplicity as well as effectiveness of rings. Our design can be a hierarchical ring interconnect that will keep all the simplicity of conventional ring patterns while reaching high scalability as more complex buffered hierarchical ring designs. We propose a router design and also show these types of routers will be significantly simpler, additional area and power efficient compared mesh based routers. In this work, we all establish the conventional error rates of the on-chip and also designed suitable Error Correction Code (ECC) mechanisms to improve their reliability. We show that using the planned specific ECC method it is easy to achieve significantly reduced power dissipation and high performance in the NoC.